Google's In-House Designed Tensor G5 SoC Tapes Out Successfully at TSMC with 3 nm Process Technology

Taiwan, Taiwan Province Taiwan, Province of China[a]
Google aims to achieve comprehensive control from the processor to the operating system, applications, and devices with its first fully in-house design for a mobile processor.
Google's next-generation Tensor System on Chip (SoC) has successfully taped out and is ready for the next phase of development.
The Tensor G5 chipset is anticipated to bring significant improvements in performance, battery optimization, and AI capabilities.
TSMC's advanced 3 nm process technology is expected to significantly enhance performance and power efficiency.
Google's In-House Designed Tensor G5 SoC Tapes Out Successfully at TSMC with 3 nm Process Technology

Google's Next-Gen Tensor SoC Tapes Out Successfully at TSMC

According to recent reports, Google's next-generation Tensor System on Chip (SoC) has successfully taped out and is now ready for the next phase of development. The chip, which will be manufactured by Taiwan Semiconductor Manufacturing Company (TSMC) using their latest 3 nm process technology, is expected to significantly boost performance compared to its predecessor.

Google's In-House Design

The Tensor G5 SoC marks Google's first fully in-house design for a mobile processor. Previous generations of Tensor chips were based on Samsung Exynos SoCs. With the new design, Google aims to achieve comprehensive control from the processor to the operating system, applications, and devices.

Manufacturing with TSMC's 3 nm Process Technology

TSMC's advanced 3 nm process technology is expected to significantly enhance performance and power efficiency. The smaller chip size allows for more transistors to be integrated, increasing the chipset's capabilities for computing tasks.

Performance Improvements and Battery Optimization

The Tensor G5 chipset is anticipated to bring significant improvements in performance, battery optimisation, and AI capabilities. These enhancements will enable Google to offer a better user experience with its upcoming Pixel 10 series smartphones.

Sources: [1] Ctee.com - Google Tensor G5 SoC tapes out on TSMC's latest 3 nm node [2] Technode - Google's Tensor G5 processor to enter tape-out stage, manufactured with TSMC's 3nm process [3] Gadgets360 - Google Reportedly Completes Design Process for Its Tensor G5 Chipset



Confidence

90%

Doubts
  • Are there any specific benchmarks or tests that confirm the performance improvements of the Tensor G5 SoC?
  • Is Google's in-house design a complete replacement for Samsung Exynos SoCs, or just for mobile processors?

Sources

100%

  • Unique Points
    • Google’s Tensor G5 SoC has successfully taped out and is ready to enter the next phase of development.
    • The Tensor G5 will be manufactured by TSMC using their latest 3 nm process technology.
    • Google is designing the chip from scratch for its upcoming Pixel 10 series.
  • Accuracy
    No Contradictions at Time Of Publication
  • Deception (100%)
    None Found At Time Of Publication
  • Fallacies (100%)
    None Found At Time Of Publication
  • Bias (100%)
    None Found At Time Of Publication
  • Site Conflicts Of Interest (100%)
    None Found At Time Of Publication
  • Author Conflicts Of Interest (100%)
    None Found At Time Of Publication

99%

  • Unique Points
    • The Pixel 10 is expected to be released in late 2025.
    • Google might introduce the Tensor G5 chip with the Pixel 10.
    • An ultrasonic fingerprint sensor could be included in the Pixel 10.
    • Camera enhancements are anticipated for the Pixel 10.
    • Google is expected to integrate more machine learning features into the Pixel 10.
    • The starting storage for all models of the Pixel 10 might be increased to 256 GB, and an option for 512 GB could be available.
    • Regarding RAM, it’s believed that the standard model should have 12 GB instead of the current 8 GB.
  • Accuracy
    No Contradictions at Time Of Publication
  • Deception (100%)
    None Found At Time Of Publication
  • Fallacies (100%)
    None Found At Time Of Publication
  • Bias (100%)
    None Found At Time Of Publication
  • Site Conflicts Of Interest (100%)
    None Found At Time Of Publication
  • Author Conflicts Of Interest (0%)
    None Found At Time Of Publication

98%

  • Unique Points
    • TSMC reportedly completes tape-out for next-gen Google Tensor SoC (unique to the given article)
  • Accuracy
    No Contradictions at Time Of Publication
  • Deception (100%)
    None Found At Time Of Publication
  • Fallacies (100%)
    None Found At Time Of Publication
  • Bias (100%)
    None Found At Time Of Publication
  • Site Conflicts Of Interest (100%)
    None Found At Time Of Publication
  • Author Conflicts Of Interest (100%)
    None Found At Time Of Publication

100%

  • Unique Points
    • Google is developing the Tensor G5 processor for its tenth generation Pixel series smartphones.
    • The Tensor G5 processor will be manufactured using TSMC’s 3nm process technology.
    • The Tensor G5 is Google’s first fully self-developed mobile processor.
    • Manufacturing the Tensor G5 using TSMC’s advanced 3nm process is expected to significantly boost performance.
  • Accuracy
    No Contradictions at Time Of Publication
  • Deception (100%)
    None Found At Time Of Publication
  • Fallacies (100%)
    None Found At Time Of Publication
  • Bias (100%)
    None Found At Time Of Publication
  • Site Conflicts Of Interest (100%)
    None Found At Time Of Publication
  • Author Conflicts Of Interest (100%)
    None Found At Time Of Publication

100%

  • Unique Points
    • Google’s Tensor G5 chipset design process is complete and ready for fabrication at Taiwan Semiconductor Manufacturing Company (TSMC)
    • The Tensor G5 chipset, expected to debut with Google Pixel 10 series in 2025, is developed fully by Google instead of being based on a Samsung Exynos SoC
    • Google has reached an agreement with TSMC for the fabrication of Tensor G5 using second-generation 3nm node (N3E)
    • Pixel 10 series is expected to have better battery optimisation and thermal management with the customised chipset
  • Accuracy
    No Contradictions at Time Of Publication
  • Deception (100%)
    None Found At Time Of Publication
  • Fallacies (100%)
    None Found At Time Of Publication
  • Bias (100%)
    None Found At Time Of Publication
  • Site Conflicts Of Interest (100%)
    None Found At Time Of Publication
  • Author Conflicts Of Interest (0%)
    None Found At Time Of Publication