Samsung Electronics is considering the application of 3D chiplet technology to its Exynos mobile application processors (APs).
Samsung is developing its own chip packaging solution, SAINT (Samsung Advanced Interconnection Technology), to compete with TSMC's CoWoS (Chip-on-Wafer-on-Substrate) technology.
Samsung is reportedly starting to use a new chip packaging technology, FOWLP (Fan-Out Wafer Level Packaging), which improves chip performance and reduces power consumption.
Samsung Electronics is reportedly developing a range of advanced chip packaging solutions to enhance the performance and efficiency of its semiconductor products. The company's new technology, known as SAINT (Samsung Advanced Interconnection Technology), is being designed to compete with TSMC's CoWoS (Chip-on-Wafer-on-Substrate) technology.
In addition to SAINT, Samsung is also considering the application of 3D chiplet technology to its Exynos mobile application processors (APs). This next-generation packaging technology involves manufacturing semiconductors with different functions and connecting them into a single chip, which could reduce overall package size and increase bandwidth and power efficiency.
Furthermore, Samsung is reportedly starting to use a new chip packaging technology, FOWLP (Fan-Out Wafer Level Packaging), which improves chip performance and reduces power consumption. This technology is expected to be used in the Exynos 2400, potentially improving power efficiency and reducing size, which have been issues with previous Exynos chips. The Exynos 2400 will be used in the Galaxy S24 and the Galaxy S24+ in most countries.
Samsung's advancements in chip packaging technology are not only expected to enhance the performance and efficiency of its own products but also make them more competitive with offerings from other tech giants such as Qualcomm and Apple. Other companies like NVIDIA, AMD, and Intel are also exploring chiplet technology, indicating a broader industry trend towards these advanced packaging solutions.
Compared to the current packaging technology (FC-BGA or Flip Chip-Ball Grid Array), chips using FOWLP are 40% smaller, 30% thinner, and deliver 15% greater performance.
The Exynos 2400 AP, built by Samsung Foundry using its second-generation 4nm process node (4LPP), is expected to use FOWLP chip packaging technology to improve power efficiency and reduce the chipset's size.
Samsung is developing its own chip packaging solution, SAINT (Samsung Advanced Interconnection Technology), to compete with TSMC's CoWoS (Chip-on-Wafer-on-Substrate) technology.
Samsung is also reportedly competing to win a large order of HBM memory to power NVIDIA's next-gen Blackwell AI GPUs.
The company recently introduced its Shinebolt 'HBM3e' memory.
Samsung Electronics is considering the application of 3D chiplet technology to its Exynos mobile application processors (APs).
3D chiplets could reduce overall package size and increase bandwidth and power efficiency, making Exynos APs more competitive with Qualcomm and Apple offerings.
Other companies like NVIDIA, AMD, and Intel are also exploring chiplet technology.